The present invention relates to a semiconductor device and a manufacturing method of the same.
For a logic device such as a CPU, an SRAM having good consistency in logic process is used as a main memory, and an SRAM that operates at a low voltage is desired for achieving lower power consumption of the device.
On the other hand, in a logic circuit part, in addition to the low-voltage operation, low-load capacity is an important factor for realizing the lower power consumption of the device.
The most major factor that determines the low-voltage operation margin of the microfabricated SRAM is variance of threshold voltage due to variations in impurities.
The variance of threshold voltage σVt is given by the following equation (1) (see p. 279, Fundamentals of Modern VLSI Devices written by Taur and Ning).σVt=q√(Na·Wdm0/(3LW))/Cox  (1)
Note that, in the equation (1), L is a gate length of a transistor, W is a gate width of the transistor, Na is channel impurity density, and Wdm0 is a channel depletion layer width. Further, Cox is gate capacity.
The variance of threshold voltage σVt of the microfabricated MOSSFET having a small gate length L and a gate width W is suppressed in the following manner. For example, from the equation (1), a high-dielectric material such as hafnium oxide (HfO2) and hafnium silicide oxynitride (HfSiON) is used for a gate insulating film and the film thickness Tox of the effective gate insulating film is made smaller. Alternatively, a fully-depleted SOI transistor (the threshold voltage Vt is not determined by Na but Vt is determined by a work function of the gate electrode material) is used (e.g., see C. Fenouillet-Beranger, et al., “Fully-Depleted SOI Technology using High-K and Single-Metal Gate for 32 nm Node LSTP Applications featuring 0.1 79 μm2 6T-SRAM bitcell”, 2007 IEDM 10.7.
However, even when a High-K film is used for the gate insulating film, Tox is not significantly reduced, and σVt eventually becomes a problem as scaling progresses.
In C. Fenouillet-Beranger, et al., an example of a 6T-SRAM using a fully-depleted SOI·FET is shown. For the FET, a high-dielectric (High-K) gate insulating film and a metal gate are used. In this way, σVt can be made smaller by making Tox effectively smaller using the High-K film.
Specifically, right and left gates of an access transistor are independent and Vt of the access transistor is changed at reading out (High Vt) and writing (Low Vt) using a gate terminal for driving force adjustment. The Fin-FET is a vertical fully-depleted double-gate transistor, and the impurity density Na of the channels can take a small value by appropriate selection of the gate electrode material and σVt can be made smaller as a result.
However, since the transistor structure is vertical, microfabrication of the gate electrode, ion implantation, formation of a diffusion layer, formation of a sidewall spacer, formation of salicide are difficult. Further, connection is made in a contact part with only a thin Si end, and the contact resistance is high. As a method of reducing the contact resistance, there is a method of epitaxially growing Si on the surface of the Si column for thickening only the connection part to the diffusion layer. However, the parasitic capacity between the gate electrode and the diffusion layer becomes larger, and the switching speed of the transistor becomes slower and the power consumption becomes higher.
As another example in related art, one in which a channel part is sandwiched by upper and lower gate electrodes, a DC bias is applied to the lower gate electrode, and the threshold voltage of the SW transistor is variably controlled is disclosed (e.g., see JP-2001-127300).
However, the example has a configuration in which independent control gates are provided on the rear surface of the BOX layer of the SOI substrate and the threshold voltage is adjusted with respect to each transistor, and, in order to reduce the variance of threshold voltage, it is necessary to optimize the gate bias on the rear surface with respect to each transistor. Accordingly, the circuit size becomes larger.
Further, as another example in related art, one in which integration is improved by vertically stacking PFETs of a two-input NAND circuit is disclosed. Note that, in the case of a two-input NOR circuit, NFETs are vertically stacked. The upper and lower gate electrodes are completely independently operated (e.g., see JP-08-288400).
The improvement in integration is intended by vertical stacking of two-input parallel transistors, however, different potentials are provided to the upper and the lower transistors, and thus, it is difficult to stabilize the potential of the common channel part and to realize the intended performance.